MaRS, a combinator graph reduction multiprocessor

Abstract

The MaRS machine is an experimental modular distributed control multiprocessor, for parallel graph reduction, using a combinator machine language, and dedicated to the parallel execution of purely functional languages. A basic programming language for the machine, named MaRS Lisp, has been defined, the main features of which are: call-by-need (default), higher order functions, implicit curryfication of functions. It includes a simple mechanism to express parallelism, similar to the future construction of Multilisp [15]. A prototype of MaRS is currently being designed in VLSI 1.5-micron CMOS technology with two levels of metal, by means of a CAD system. The prototype is scheduled to be completed by 1989. The machine uses specific types of processor for Reduction, Memory and Communication. The Communication processor is the basic element of an Omega switching interconnection network. In addition to its routing function, the communication network is able to balance the activities in the machine, thanks to charge information processed by each Communication processor and propagated along the network, in the opposite direction of messages. This charge information also serves to modify dynamically the execution model, so as to resume execution in a sequential manner when the parallelism is high enough to keep each reduction processor fully busy; and vice versa, so as to allow creation of new parallel processes when the machine is not saturated. The machine architecture and its functional organization are described, as well as the execution model. Some expected performances are given, obtained by mean of fine-grained simulations.