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Book Chapter

Timing closure

Springer International Publishing, (2016), 165-175
DOI: 10.1007/978-3-319-42438-5_14
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APA

Dasasathyan, S. (2016). Timing closure. In Designing with Xilinx® FPGAs: Using Vivado (pp. 165–175). Springer International Publishing. https://doi.org/10.1007/978-3-319-42438-5_14

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