Design and Implementation of Viterbi Decoder Using VHDL

Abstract

A digital design conversion of Viterbi decoder for 1/2 rate convolutional encoder with constraint length k = 3 is presented in this paper. The design is coded with the help of VHDL, simulated and synthesized using XILINX ISE 14.7. Synthesis results show a maximum frequency of operation for the design is 100.725 MHz. The requirement of memory is less as compared to conventional method.