Abstract
In this paper, we propose the fastest binary multiplication algorithm on 4-LUT FPGAs. Our key idea is k-bit compaction, in which the n-bit multiplier is divided into n k digits in 2k -nary’s, then the multiplicand is multiplied with each digit into a middle-product. And our second idea is oneminus- one encoding for the redundant binary representation. We’ve compared 2-bit, 3-bit and 4-bit compactions. And we have been able to construct 16-bit and 24-bit binary multipliers in 11 levels and 13 levels of 4-LUTs, respectively.
Cite
CITATION STYLE
Miomo, T., Yasuoka, K., & Kanazawa, M. (2000). The fastest multiplier on FPGAs with redundant binary representation. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 1896, pp. 515–524). Springer Verlag. https://doi.org/10.1007/3-540-44614-1_56
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