A comparative study of two different FPGA-based arrhythmia classifier architectures

Abstract

Early diagnosis of dangerous heart conditions is very important for the treatment of heart diseases and for the prevention of sudden cardiac death. Automatic electrocardiogram (ECG) arrhythmia classifiers are essential to timely diagnosis. However, most of the medical diagnosis systems proposed in the literature are software-based. This work focused on the hardware implementation of a mobile artificial neural network (ANN)-based arrhythmia classifier that is implemented on a field programmable gate array (FPGA) as a single chip solution, as an alternative to various software models of ANNs. Due to the parallel nature of ANNs, hardware implementation of ANNs needs a large amount of chip resources. In order to create an ANN structure in an FPGA, the dimensions of the ANN structure must be reduced; therefore, a data reduction algorithm was employed in the training phase and ECG features and consequently the ANN structure size was reduced with principal component analysis. An eight-input ANN-based arrhythmia classifier that has one hidden layer with two neurons and one output layer with one neuron was implemented on a single-chip FPGA. In this work, two different classifiers were consequently implemented in both 32-bit floating and 16-bit fixed point numerical representations on the same FPGA.