Practical implementations of non-blocking synchronization primitives

Abstract

This paper is concerned with system support for non-blocking synchronization in shared-memory multiprocessors. Many non-blocking algorithms published recently depend on the Load-Linked (LL), Validate (VL), and Store-Conditional (SC) instructions. However, most systems support either Compare-and-Swap (CAS) or a weak form of LL and SC that imposes several restrictions on the use of these instructions and does not provide the exact semantics expected and assumed by algorithm designers. These limitations currently render several recent non-blocking algorithms inapplicable in most systems. The results presented here eliminate this problem by providing practical means for implementing any algorithm that is based on these instructions on any multiprocessor that provides either CAS or a form of LL and SC that is sufficiently weak that it is provided by all current hardware implementations of these instructions. This is achieved in two steps. First, we propose a slight modification to the interface for LL, VL, and SC, which will not greatly impact programmers. We then exploit this modification to provide time-optimal, space-efficient implementations of the desired primitives using commonly available ones.