Parallel symbol timing recovery using FPGA for 600 Msps QPSK

Abstract

This paper presents an efficient parallel symbol timing architecture for high data rate communications receivers. The presented architecture relies on a modified version of the classic Gardner loop, and it features a “multi-channel pipeline” interpolator that enables the symbol rate to be several times higher than the clock rate of the FPGA, hence maximize the achievable throughput. The presented timing recovery scheme is demonstrated on a Xilinx XC7VX690T FPGA at 150 MHz clock rate together with an ADC at 4.8 GHz sampling rate, for an QPSK data-stream at 600 Msps symbol rate. Also, it is observed the presented scheme occupies only 2% of the logic, storage and computational resources in the targeted FPGA. With minor modifications, our algorithm may be adapted for other Amplitude-Phase modulation constellations such as 8PSK, 16PSK or QAM.