Architectural implications of hardware-accelerated bucket rendering on the PC

Abstract

Bucket rendering is a technique whereby a scene is sorted into screen-space tiles and each tile is rendered independently in turn. We expect hardware-accelerated bucket rendering to become available on the PC, and in this paper we explore the effect of such accelerators on main memory bandwidth, bus bandwidth to the accelerator, and on increased triangle set-up requirements. The most important impact is due to the fact that in general primitives overlap multiple buckets, which is a direct cause of overhead. In this paper we evaluate bucket rendering that uses the most common algorithm for bucket sorting, one based on screen-aligned primitive bounding boxes. We extend previous techniques for analytically evaluating bounding box overlap of buckets, and together with experimental results use these to evaluate accelerators that may support 32×32 pixel tiles, and those that may support 128×128 pixel tiles. We expect the former to be possible with dense SRAM, the latter to be possible with DRAM embedded in a logic process (embedded DRAM). Our results suggest that embedded DRAM implementations can support bucket rendering with bounding box bucket sorting, but that SRAM implementations will likely be at risk with respect to overall system performance when bounding box bucket sorting is employed. These results suggest the requirement for more precise but still low-overhead bucket sorting algorithms when bucket rendering hardware is constrained to 32×32 tiles.