A task scheduling algorithm for the parallel expression evaluation in a reconfigurable fully digit on-line network

Abstract

In this paper, we present a task scheduling algorithm which accounts for digit-level pipelines of on-line arithmetic units when a limited number of heterogeneous on-line arithmetic units can be connected totally with each other and the network is reconfigurable during the execution. In on-line arithmetic, an arithmetic unit can be reused after the completion of its computing process while its result is available digit by digit during the computation. Thus, a new criterion, called the maximal delay is introduced to take into account additional precedence constraints based on the on-line delay.