High Performance Buffer with Body Biasing Technique

Abstract

A buffer for reducing the power dissipation and delay for the interconnects is proposed. Body biasing is applied to increase the speed and reduce the power dissipation of the buffer. The proposed buffer is designed and implemented at 22 nm technology node. By using Spice simulations, delay and power dissipation performances are analyzed for various voltages and loading conditions. The proposed buffer has higher speed and lesser power dissipation than the conventional buffer. The proposed buffer also has lesser number of transistors compared to the other buffers designed. The proposed buffer is suitable for critical path in the interconnects and has the capability of driving large loads at sub-threshold region.