Comparing register-transfer-, C-, and system-level implementations of an image enhancement algorithm

Abstract

This paper reports on a color image enhancement algorithm implemented on a reconfigurable SoC of the Xilinx Zynq family. The algorithm consists of histogram equalization followed by an unsharp masking filter. A pure software implementation running on the Zynq’s ARM Core- A9 processor is compared to several hardware-accelerated versions with respect to the design effort and the quality-of-results. The accelerators are specified at register-transfer level, at high-level (C functions) and at system-level using the recently released Xilinx SDSoC tool. The latter approach is purely software-defined and generates all the interface code and circuitry automatically. Nevertheless, experience with high-level synthesis tools and a basic understanding of hardware coprocessor principles are also required in this approach to effectively use SDSoC. The results show that the same, significant speedup as with manual implementation can be reached for our application, but the resulting circuit tends to be larger with the higher-level design tools.