Performance analysis of scaler SoC for 4K video signal

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Abstract

This paper considers some issues to implement the scaler SoC. Because the size and power of SoC are constrained, the bit number to represent the coefficients of scaler kernel and LPF should be limited. In addition, the interpolation position should be located at the quantized phases. We analyze the effects of the various constraints in the performance of scaling system. The simulation results provide the guidance to implement the scaler SoC.

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APA

Lee, S. J., & Han, J. K. (2015). Performance analysis of scaler SoC for 4K video signal. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 9315, pp. 285–291). Springer Verlag. https://doi.org/10.1007/978-3-319-24078-7_28

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