High-performance CMOS CCI in a 0.35 μm CMOS technology and a new all-pass lter application

Abstract

A differential pair-based, high-performance, rst-generation current conveyor is proposed. The proposed circuit is laid out using the Mentor Graphics IC Station layout editor. The performance characteristics have been determined from HSpice postlayout simulations using the Austria Mikro Systeme 0.35 μm, 3.3 V process parameters. During the simulations, ±1.65 V supply voltages and a 25 μA biasing current are used. The power consumption is about 1.12 mW. The circuit also has very high voltage swings on ports X and Y, a very small impedance value on port X, high impedance values on ports Y and Z, and high-valued current and voltage transfer bandwidths. It is shown that the presented circuit can satisfy both the low-voltage/low-power and high-frequency performance current conveyor needs of the analog circuit applications. Furthermore, 2 new all-pass lter circuits as application examples are given and a procedure that can be used to search for the opportunities that would result from the use of the modied current conveyors is presented. Some special circuit topologies and new circuit function possibilities can be obtained by redesigning circuits with modied current conveyors, which is not possible with a standard current conveyor. The proposed approach is expected to allow deeper insight into circuit synthesis using modied current conveyors.