On an implementation of the mohan-adiga algorithm

Abstract

Several asymmetric cryptographic systems such as the RSA system [6] require modular exponentiation of large integers. This paper discusses a modular routine described in [2], which is suited for smart cards. It is based on the Mohan-Adiga algorithm [5]. This algorithm is comparatively fast, if the leading half of the bits of the modulus is -1. It will be shown that this restriction has some severe implications on the number of suitable primes and on the security of the system. If one decrements the number of leading 1’s then the security level of the system is increased while the speed is decreased.