Implementation of area optimized low power multiplication and accumulation

Abstract

There is number of computations involved at every stage in Digital Signal Processing (DSP). At every stage of computation we have addition and multiplication of the terms derived from previous and presents stages. The general computation incorporates the use of normal multiplication and addition, but the circuitry of normal multiplication and addition is lethargic i.e., it consumes more space on chip, consumes more power and the speed of computation is also low.These drawbacks can be avoided by switching to proposed method called Multiplication and Accumulation (MAC). Aim of this project is to develop an Area optimized Low power digital circuit for MAC (Multiply and Accumulate) operation. We develop the Verilog Hardware Description Language code for the various implementations of the MAC (Multiply and Accumulate) that is we try to avoid using multipliers and prefer to use the combinational circuits like multiplexers. These Verilog HDL codes will be simulated to check the functionality. Once we get the expected results we go for the implementation of the digital circuits. We analyze all the MAC digital circuits to find out the best digital circuit which consumes minimum area and power. The importance of MAC in FPGA designs is explained by some filter designs. We also give some suggestions on the system level solutions based on the MAC.