Negative Bias Temperature Instability in Nanoscale Devices

Abstract

In this Chapter we focus on the NBTI of nanoscale SiGe pFETs and compare with the results obtained on large area devices. In particular, we assess the impact of individually trapped charges on the characteristics of SiGe devices with varying Si cap thicknesses, since this gate-stack parameter was found to be crucial for the standard NBTI reliability on large area devices. The use of a SiGe channel is shown to offer a considerable reliability improvement also for deeply-scaled devices. We discuss how the observed improvement is expected to yield a significantly alleviated time-dependent variability of a realistic device population (billions of devices). Furthermore, we show that the impact of individual charged defects on the device characteristics scales reciprocally with the device area, and we demonstrate the measurement of the entire ID-VG characteristic of planar pMOSFETs before and after the capture of a single hole. Finally, the body bias is shown to modulate the impact of individual charged gate oxide defects on the device characteristics. © Springer Science+Business Media Dordrecht 2014.