High Speed Cache Design Using Multi-diameter CNFET at 32nm Technology

Abstract

This paper proposes a high-speed multi-diameter CNFET-based 7T (seven transistor) SRAM (static random access memory) cell. It investigates the impact of process, voltage and temperature (PVT) variations on its design metrics and compares the results with its counterpart - CMOS-based 7T SRAM cell. The proposed design offers 77.4× improvement in write access time along with 88.1× reduction in write access time variation and 117.8× saving in write power along with substantial reduction in write EDP/write EDP variation. The proposed memory cell shows 40% improvement in SNM (static noise margin) and better robustness against PVT variations. © Springer-Verlag Berlin Heidelberg 2010.