Bit-serial AOP arithmetic architectures over GF(2m)

Abstract

This paper presents bit-serial arithmetic architectures for GF(2m) based on an irreducible all one polynomial. First, modular multiplier and squarer are designed. Then, two arithmetic architectures are proposed based on the modular multiplier and squarer. Proposed architectures hybrid the advantages of hardware and time complexity from previous architectures. They can be used as kernel architecture for modular exponentiations, which is very important operation in the most of public key cryptosystem. Since the multipliers have low hardware requirements and regular structures, they are suitable for VLSI implementation.