Self-aligned asymmetric metal-oxide-semiconductor field effect transistors fabricated on silicon-on-insulator

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Abstract

We have fabricated the sub-30nm asymmetric n-channel metal-oxide- semiconductor field effect transistors (NMOSFETs) and investigated its operation and characteristics. In this work, two key ideas are newly introduced in order to improve the device performance. One is the introduction of silicon-on-insulator (SOI) substrate to remove junction leakage paths. The other is the modification of mask layout for performance optimization and mass production. By using SOI substrate and modifying mask layout, the ON/OFF current ratio of the fabricated device is quite increased when we compared with the previous work because the source/drain junction leakage and parasitic current are suppressed. Moreover, the fabricated device has excellent scaling properties in terms of short channel effect. © 2009 The Japan Society of Applied Physics.

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Kim, J. P., Song, J. Y., Kim, S. W., Park, J. H., Choi, W. Y., Lee, J. D., … Park, B. G. (2009). Self-aligned asymmetric metal-oxide-semiconductor field effect transistors fabricated on silicon-on-insulator. Japanese Journal of Applied Physics, 48(9 Part 1), 0912011–0912015. https://doi.org/10.1143/JJAP.48.091201

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