Implementation of high secured low power advance encryption standard (AES) implementation with DNA cryptography

Abstract

The power reduction attacks are a class of side medium attacks depends on the utilization of power. We present the secure dual rate register (SDRR) to the regular advance encryption standard (AES-128), it improves the safety of the cryptography devices against power reduction attacks. The proposed method doesn’t need the replicating of data to process irregular information. The rear progression in cryptography has prompted a new method called DNA based cryptography. We proposed a secure dual rate register to the regular AES-128 with DNA cryptography. Design flow is synthesized using Xilinx ISE software to create a simple digital circuit using Verilog HDL and with 22nm technology was used to reproduction the utilizing Verilog.