High Voltage Stress Impact on P Type Crystalline Silicon PV Module

Abstract

The effects of the high voltage stress and other environmental conditions on crystalline silicon photovoltaic module performance have not been included in the IEC 61215 or other qualification standards. In this work, we are to evaluate the potential induced degradation on p type crystalline silicon PV modules by three cases, one case is in room temperature, 100% relative humidity water bath, another is in room temperature, the front sheet coverage with aluminum foil and the other is in the 85°C, 85% relative humidity climate chamber. All the samples are applied with the -1000 V bias to active layers, respectively. Our current-voltage measurements and electroluminescence results showed in these modules power loss of 37.74%, 11.29% and 49.62%, respectively. These test results have shown that among high voltage effects the climate chamber is the harshest and fastest test. In this article we also showed that the ethylene vinyl acetate volume resistivity and soda-lime glass ingredients are important factors to PID failure. The high volume resistivity which is more than 1014 Ω·cm and Na less contents glass will mitigate the PID effect to ensure PID free.