Exploring the platform for expressing systemverilog assertions in model based system engineering

Abstract

Despite the importance of Model Based System Engineering (MBSE) for early design verification, it is always challenging to represent the system properties/constraints at higher abstraction level due to complex behavioral and temporal aspects of embedded systems. To manage this, OCL (Object Constraint Language) and CCSL (Clock Constraint Specification Language) have been frequently used. On the other hand, SystemVerilog is a renowned hardware design and verification language that supports Assertion Based Verification (ABV). However, no real efforts have been made to employ SystemVerilog Assertions (SVA’s) in MBSE. In this paper, we explore various possibilities to represent SVA’s at higher abstraction level. Firstly, we evaluate the existing property specification approaches to represent SVA’s at higher abstraction level. Consequently, we select OCL as an appropriate approach. Secondly, we investigate the syntax and semantics of OCL in the context of SVA’s. The outcomes of research provide the sound platform to represent SVA’s in OCL for model-based design verification of embedded systems.