Scalable Karatsuba multiplier over finite field GF (2m )

Abstract

A scalable architecture for efficient multiplication in finite fields GF (2 m ) was proposed. The proposed design had symmetric form with 64 × 64-bit inputs, supporting with any finite fields GF (2m ), where m < 320, and almost all irreducible polynomials. Due to the introduced fast unbalanced modular reduction method and Karatsuba like algorithm, fast operation was obtained. Unlike the most proposed bit-serial or digit-serial multiplier, data access of the symmetric multiplier was in accordance with the memory access pattern. And it also can be developed to meet the requirement of any GF (2 m ), where m > 320, through tiny change of control logic and register file. The analysis result showed it may improve the operation performance by 50 % over the NIST recommended curve of GF (2283) comparing with another original method. © 2013 Springer-Verlag.