A novel methodology to ameliorate the transient loading of low dropout regulators (LDRs)

Abstract

A new simple and mathematically based design methodology, which makes LDR output nearly insensitive to overshot or undershot jumps of the load current for long times, is proposed. This methodology is categorized on two stages. The first stage is the characterization of the LDR power transistor in the transient mode through the modeling of its terminal currents in terms of the normalized inversion charge density. As a completion of this stage, the channel charge density is computed in terms of the transistor terminal voltages by means of a charge-voltage compact MOS model. Based on this stage, the second one tends to represent the LDR in the transient loading conditions as a current mode feedback stabilizer for the floating terminal voltages of the LDR output transistor. The suggested procedure leans on cross coupling of the time second derivative of the LDR power transistor gate and drain voltages as well as currents. The power transistor transient terminal currents are modeled by the integral form of partial differential continuity equation where the channel charge density is linearly spatial approximated in terms of its boundary conditions. These boundary conditions are modeled in terms of the transistor terminal currents via EKV charge based compact model. The introduced methodology is applied to a standard CMOS of 0.18µm technology for NMOS power transistor which involved within a proposed negative LDR system that is validated using MATLAB R2014a. This technique realizes a pseudo static output keeping low values of the crossly coupled currents in order of nano Ampere or hundreds of micro Ampere for undershot or overshot cases, respectively, for a time period of more than 104 seconds. The proposed procedure figures out the principle of realizing a transient mode hardware of LDRs. This hardware can be coincided with the design requirements of LDRs in static and small signal dynamic modes.