New challenges for designers of fault tolerant embedded systems based on future technologies

Abstract

The major challenges that will be faced by designers of embedded systems based on future technologies are discussed. While providing many benefits, those technologies bring along several problems, such as higher defect rates, higher sensitivity to radiation induced transient faults, and the possibility of occurrence of multiple simultaneous faults and long duration transients. The main characteristics of future technologies are presented and the new challenges imposed to designers highlighted. Classic and recently proposed mitigation techniques are reviewed and the weaknesses that will impair their application to those technologies discussed. Recent research works aiming to cope with this new scenario are presented, analyzed and discussed, taking into account their impact on area, performance and power consumption. Strategies to cope with those challenges at different design levels are discussed and research paths that may lead to the solution of the problems are proposed.