An analog CMOS neural network with on-chip learning and multilevel weight storage

Abstract

An analog neural network with four neurons and 16 synapses, fabricated in a 1.2 μm n-well single-polysilicon, double-metal process, is presented. The circuit solutions adopted, for on-chip learning and weight storage, particularly simple and silicon area-efficient, are capable of solving the main problems to the implementation of analog neural networks.