Macroservers: An object-based programming and execution model for processor-in-memory arrays

Abstract

The emergence of semiconductor fabrication technology allowing a tight coupling between high-density DRAM and CMOS logic on the same chip has led to the important new class of Processor-in-Memory (PIM) architectures. Recent developments provide powerful parallel processing capabilities on the chip, exploiting the facility to load wide words in single memory accesses and supporting complex address manipulations in the memory. Furthermore, large arrays of PIMs can be arranged into massively parallel architectures. In this paper, we outline the salient features of PIM architectures and describe the design of an object-based programming and execution model centered on the notion of macroservers. While generally adhering to the conventional framework of object-based computation, macroservers provide special support for the efficient control of program execution in a PIM array. This includes features for specifying the distribution and alignment of data in virtual object space, the binding of threads to data, and a future-based synchronization mechanism. We provide a number of motivating examples and give a short overview of implementation considerations.