Semi-systolic architecture for modular multiplication over GF(2 m)

Abstract

This paper proposes a new algorithm and an architecture for it to compute the modular multiplication over GF(2m). They are based on the standard basis representation and use the property of irreducible all one polynomial as a modulus. The architecture, named SSM(Semi-Systolic Multiplier) has the critical path with 1-DAND+1-DXOR per cell and the latency of m+1. It has a lower latency and a smaller hardware complexity than previous architectures. Since the proposed architecture has regularity, modularity and concurrency, they are suitable for VLSI implementation. © Springer-Verlag Berlin Heidelberg 2005.