An efficient multi-processor architecture for parallel cyclic reference counting

Abstract

Multi-processor architectures are part of the technological reality of today. On the other hand, the software engineering community reached the consensus that memory management has to be performed automatically, without the interference of the programmer of applications. Reference counting is the memory management technique of most widespread use today. This paper presents a new architecture for parallel cyclic reference counting. © Springer-Verlag Berlin Heidelberg 2003.