FPGA based power saving technique for sensor node in wireless sensor network (WSN)

Abstract

The demand for high-performance WSN is increasing and its power consumption has threatened the life of the WSN. In WSN, different factors are affecting the power consumption like sensor node, communication protocols and packet data transfer. After power analysis of WSN, it is identified that reduction in power consumption of sensor nodes is vital in WSN. Nowadays, FPGA configurable architecture becomes attractive solutions to design the sensor node due to its advanced features. The proposed system presents the design and implementation of power saving technique for wireless sensor node with power management unit (DVFS + Clock gating) controlled by cooperative custom unit with parallel execution capability on FPGA. The customizable cooperative unit is based on customization of Operating System (OS) acceleration using dedicated hardware and apply it to soft core processor. This unit will reduce OS CPU overhead involved in processor based sensor node implementation. The power management unit performs functionalities like control the clock of the soft processor, hardware peripherals and put them in proper state based on hardware requirement of application (tasks) under execution. Additionally, there is a need to dynamically scale the voltage and frequency by considering control signals from cooperative custom unit. In this proposed work, the performance and power consumption of FPGA-based power saving technique for sensor node can be compared with the power consumption in the processor based implementation of sensor nodes. The proposed work aims to design efficient power saving techniques for wireless sensor node using FPGA configurable architecture.