Abstract
This paper presents new speed records for AES software, taking advantage of (1) architecture-dependent reduction of instructions used to compute AES and (2) microarchitecture-dependent reduction of cycles used for those instructions. A wide variety of common CPU architectures-amd64, ppc32, sparcv9, and x86-are discussed in detail, along with several specific microarchitectures. © 2008 Springer Berlin Heidelberg.
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CITATION STYLE
Bernstein, D. J., & Schwabe, P. (2008). New AES software speed records. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 5365 LNCS, pp. 322–336). https://doi.org/10.1007/978-3-540-89754-5_25
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