High speed network intrusion detection system using FPGA

Abstract

Modern Network Intrusion detection needs a high-speed interface to analyze the incoming packet. Several network intrusion detection applications detect multiple strings in the payload of a packet by comparing it against predefined pattern set which requires more memory and computation power. To meet this, a dedicated hardware with high processing capacity can be placed at the port of incoming packets. Field Programmable Gate Array (FPGA) is the choice as it can be programmed easily and dynamically for parallel computing. Moreover, FPGA devices support at high-speed interface and are capable of providing better processing capability than other device; also it can be reprogrammed when it is needed. This paper proposes a new alternative approach to leaf attaching algorithm to improve the memory efficiency of algorithm.