Early-estimation modeling of processors

Abstract

We are hitting power budget and power density limitations ever harder with continuing electronics miniaturization. High power density is not a new problem: CMOS technologies were adopted in the late 70s and early 80s mainly because of their lower power density in comparison to bipolar processes. This time there is no such alternative, more energy efficient technology at sight. Thus, the solution lies in methodological and archi tectural innovation for more efficient energy utilization. Intel's Senior Vice President and CTO, Patrick P. Gelsinger, has noted that for every doubling of available transistors, we have gained approximately 40% in design performance. This observation suggests that performance per transistor, and hence energy efficiency, has degraded significantly. © 2007 Springer Science+Business Media B.V.