Abstract
We have developed a set of microbenchmarks for accurately determining the structural characteristics of data cache memories and TLBs. These characteristics include cache size, cache line size, cache associativity, memory page size, number of data TLB entries, and data TLB associativity. Unlike previous microbenchmarks that used time-based measurements, our microbenchmarks use hardware event counts to more accurately and quickly determine these characteristics while requiring fewer limiting assumptions. © Springer-Verlag 2004.
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CITATION STYLE
Dongarra, J., Moore, S., Mucci, P., Seymour, K., & You, H. (2004). Accurate cache and TLB characterization using hardware counters. Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 3038, 432–439. https://doi.org/10.1007/978-3-540-24688-6_57
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