Towards high-level specification, synthesis, and virtualization of programmable logic designs

Abstract

Current FPGA design flows do not readily support highlevel, behavioural design or the use of run-time reconfiguration. Designers are thus discouraged from taking a high-level view of their systems and cannot fully exploit the benefits of programmable hardware. This paper reports on our advances towards the development of design technology that supports behavioural specification and compilation of FPGA designs and automatically manages FPGA chip virtualization.