Abstract
In this paper we discuss several key agile Camellia implementations. The New European Schemes for Signatures, Integrity, and Encryption (NESSIE) selected Camellia in its portfolio of strong cryptographic algorithms for protecting the information society. In order for an encryption core to be key agile it must be able to accept new secret keys as well as data on every clock cycle. We discuss the design and implementation of the Camellia algorithm for a FPGA. We obtain a throughput of 17.4 Gbit/sec when running on a Virtex-II XC2V4000 FPGA device. © Springer-Verlag Berlin Heidelberg 2004.
Cite
CITATION STYLE
Denning, D., Irvine, J., & Devlin, M. (2004). A key agile 17.4 Gbit/sec Camellia implementation. Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 3203, 546–554. https://doi.org/10.1007/978-3-540-30117-2_56
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