This paper proposes an analog CMOS VLSI circuit which implements integrate-and-fire spiking neural networks with spike-timing dependent synaptic plasticity (STDP). The designed VLSI chip includes 25 neurons and 600 synapse circuits with symmetric all-to-all connection STDP. Using the fabricated VLSI chip, we implement a Hopfield-type feedback network, and demonstrate its associative memory operation. In our chip, analog information is represented by the relative timing of spike firing events. Symmetric STDP provides an auto-correlation learning function depending on relative timing between spikes consisting of a learning pattern. Each learning and test pattern consists of 20 spike pulses each of which has a relative delay corresponding to a gray-scale pixel intensity. The chip has successfully associated from an input pattern the most similar learning pattern. © 2011 Springer-Verlag.
CITATION STYLE
Huayaney, F. L. M., Tanaka, H., Matsuo, T., Morie, T., & Aihara, K. (2011). A VLSI spiking neural network with symmetric STDP and associative memory operation. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 7064 LNCS, pp. 381–388). https://doi.org/10.1007/978-3-642-24965-5_43
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