AADD-based symbolic simulation of systemC AMS

Abstract

Traditional modeling languages and simulators are still separated from formal verification languages and tools. The main reason for this is that formal verification algorithms require a formal model of a system to verify its behavior. However, the automatic generation of such model requires a separate, dedicated compiler. This paper shows an approach how to use the existing simulator to generate a formal model of a system without using yet another compiler, intermediate language or tool. The approach is based on generation of AADD and BDD for symbolic simulation and it is integrated in SystemC AMS modeling language and simulator.