Compression and variable-sized ECC scheme for the reliable flash memory system

Abstract

The advances of flash memory process geometry scaledown has lead dramatic capacity increase, however, as a result, endurance is severely degraded resulting in a excessive increase of data errors. To recover the errors occurred during runtime, well known error correction codes (ECC) are integrated into flash memory controller. However, the existing error correction codes have their inherent limits to recover more error data, so more additional schemes should be considered for the higher reliable flash storage systems. In this paper, we propose an architecture for processing combined error correction schemes of compression and variable-sized ECC engine. In the error correction scheme, the original data is compressed with compression module to reduce practical data portion for ECC covered, then, the variable-sized ECC coding is done for the reduced practical data to generate more redundancies. These additional redundancies are stored in the unused area of flash memory page due to compression. The proposed scheme keeps flash memory higher reliable storage systems by dropping down nonlinear increase of bit error rates.