Microchip health monitoring system using the fll circuit

Abstract

Here a solution for a Microchip Health Monitoring (MHM) system using MTOL (Multi‐Temperature Operational Life) reliability testing assessment data is proposed. The module monitors frequency degradation over time compared to lab tested data. Since trends in performance degradation in recently developed devices have transitioned from multiple failure mechanisms to a single dominant failure mechanism, development of the monitor is greatly simplified. The monitor uses a novel circuit customized to deliver optimum accuracy by combining the concepts of ring oscillator (RO) and phase locked loop (PLL) circuits. The modified circuit proposed is a new form of the frequency locked loop (FLL) circuit. We demonstrate that the collection of frequency degradation data from the ring circuits of each test produces Weibull distributions with steep slopes. This implies that the monitor can predict accurate end‐of‐life (EOL) predictions at early stages of chip degradations. The design of the microchip health monitoring system projected in this work can have great benefit in all systems using FPGA and ASIC devices.