Multi-channel FXLMS Filter as an Array of Processing Blocks and a Method to Maintain Its Performance when Increasing the Number of Channels

Abstract

The advantage of field programmable gates arrays (FPGAs) over microprocessors is the possibility of parallel computing based on logical resources organized as a required number of parallel devices. The disadvantage of FPGAs is the risk of performance degradation of implemented devices the performance of which is based mainly on programmable interconnections between resources. The performance can also be decreased because of high signal fanouts and non-optimal positioning of separate units of the device on a chip. In the paper below, the author analyzes the architecture of FPGA-based multi-channel adaptive FXLMS filter implemented as an array of processing blocks. FXLMS filters are widely used in active noise control systems. The paper also analyzes the main reasons for reduction in filter performance if the number of channels increases and the ways of maintaining the filter performance at the level of logical FPGA resources. It is shown that the most efficient way to keep the filter performance high is to use a register tree for signal pipelining.