Abstract
Observed ADC area and power scaling do not seem to follow the trends predicted using pure technology scaling arguments. A cubic improvement in area and power with gate length is observed in literature, which has been enabled by migration towards more and more capacitor-based ADC architectures, and the introduction of digitally-assisted performance enhancement strategies to overcome component mismatch. This paper assesses these trends, and discusses the most relevant enhancement strategies for mismatch-limited ADCs. Trade-off analysis between mismatch compensation in the analog domain (digitally assisted trimming, possibly in combination with up-scaling) vs. the digital domain (digital post-distortion) is required. The increasing use of digitally enhanced ADC architectures proves to be the main driver for the observed improvement in area and power with scaling. © 2012 Springer Science+Business Media B.V.
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CITATION STYLE
Verhelst, M., Alpman, E., & Lakdawala, H. (2012). Considerations for cost-efficient calibration of scaled ADCs. In Analog Circuit Design - Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC, AACD 2011 (pp. 89–117). Kluwer Academic Publishers. https://doi.org/10.1007/978-94-007-1926-2_5
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