Abstract
We present new results concerning the integration of high level designed IPS into a complete System on Chip. We first introduce a new computation model that can be used for cycle accurate simulation of register transfer level synthesized hardware. Then we provide simulation of a SoC integrating a data-flow IP synthesized with MMAlpha and the SocLib cycle accurate simulation environment. This integration also validates an efficient generic interface mechanism for data-flow IPS. © Springer-Verlag Berlin Heidelberg 2004.
Cite
CITATION STYLE
Fraboulet, A., Risset, T., & Scherrer, A. (2004). Cycle accurate simulation model generation for SoC prototyping. Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 3133, 453–462. https://doi.org/10.1007/978-3-540-27776-7_47
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