Low-Power test pattern generation

Abstract

Test pattern generation is an important part of the VLSI testing flow that offers many possibilities that can be explored for reducing test power dissipation. The issue of test power reduction can be addressed at various stages of test generation for logic circuits, by employing low-power automatic test pattern generation, low-power test compaction, low-power X-filling, and low-power test vector ordering. In addition, power dissipation in memory testing can be reduced through low-power memory test generation. The most significant advantage of reducing test power through low-power test generation is that this approach causes neither circuit overhead nor performance degradation. However, low-power test generation is a complex technical field, in which many important factors in addition to the effect of test power reduction such as test vector count inflation, potential fault coverage loss, test generation time increase, compatibility with compressed scan testing, and test generation flow modification should be taken into careful consideration. Therefore, the objective of this chapter is to provide a comprehensive overview of the basic principals and fundamental approaches to low-power test generation, along with detailed descriptions of typical methods, so as to help researchers devise more innovative solutions and practitioners build better flows in order to achieve the goal of optimally reducing test power through low-power test generation. © 2010 Springer-Verlag US.