Design of High-IF Discrete-Time Receivers for IoT: Demystifying Aliasing Trade-Offs

Abstract

Discrete-time (DT) receiver (RX) architectures offer low-power implementation, high configurability, and easy portability to ever finer CMOS nodes. Such features are highly desirable in IoT applications. To fully explore their advantages, a deep understanding of aliasing impairments that they entail is critical. However, such a discussion has not been sufficiently explored in the literature. In this tutorial brief, we start with a DT filter, which is at the core of a DT-RX. Next, a high-intermediate-frequency (IF) architecture is chosen to demonstrate how aliasing is an intrinsic part of a DT-RX and how it affects key system design aspects. Further on, we discuss the application of decimation techniques and the stringent trade-offs involved.