Design of pipeline multiplier based on modified booth's algorithm and wallace tree

Abstract

A design of 32*32 bit pipelined multiplier is presented in this paper. The proposed multiplier is based on the modified booth algorithm and Wallace tree structure. In order to improve the throughput rate of the multiplier, pipeline architecture is introduced to the Wallace tree. Carry Select Adder is deployed to reduce the propagation delay of carry signal for the final level 64-bit adder. The multiplier is fully implemented with Verilog HDL and synthesized successfully with Quartus II. The experiment result shows that the resource consumption and power consumption is reduced to 2560LE and 120mW, the operating frequency is improved from 136.21MHz to 165.07MHz. © 2011 Springer-Verlag Berlin Heidelberg.