Synthesis of pseudorandom number generator by combining mentor graphics hdl designer and xilinx vivado fpga flow

Abstract

Pseudorandom number generators are used in cryptographic as well as VLSI testing applications. Linear Feedback Shift Registers (LFSR) are circuits that can be used as pseudorandom number generators. This paper proposes a modified reseeding method for LFSR and also presents a design flow for the implementation. The work is done by combining Mentor Graphics HDL Designer FPGA flow and Xilinx Vivado. Different bit lengths of LFSR are generated using Mentor Graphics HDL Designer and synthesized using both Mentor Graphics Precision RTL synthesizer and Xilinx Vivado. The implementation targets Virtex-7 FPGA.