Noise margin in low power SRAM cells

Abstract

Noise margin at read, at write and in stand-by is analyzed for the 6 transistor SRAM cell in a 0.18μm process considering specific low power conditions such as low supply voltage and source-body biasing. These conditions reduce the noise margin. By using an asymmetrical cell design in which read is performed only on one of the two complementary bit lines, the noise margin can be improved and the bias limits extended for a reduced power consumption. © Springer-Verlag 2004.