Abstract
We report on the design and formal verification of a complex processor supporting address translation by means of a memory management unit (MMU). We give a paper and pencil proof that such a processor together with an appropriate page fault handler simulates virtual machines modeling user computation. These results are crucial steps towards the seamless verification of entire computer systems. © IFIP International Federation for Information Processing 2005.
Cite
CITATION STYLE
Dalinger, I., Hillebrand, M., & Paul, W. (2005). On the verification of memory management mechanisms. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 3725 LNCS, pp. 301–316). https://doi.org/10.1007/11560548_23
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