Gate-level-accurate fault-effect analysis at virtual-prototype speed

Abstract

The cost of efficient fault-effect analysis on gate-level (GL) and register-transfer level models is increasing due to the rising complexity of safety-critical systems on chip (SoCs). Virtual prototypes (VPs) based on transaction-level models are employed to speed-up safety verification. However, VP structures correlate poorly to GL models. This leads to the injection of pseudo-faults into VPs and to the development of suboptimal safety mechanisms for the SoC. To mitigate these drawbacks, in this paper, we propose a safety-verification flow for VPs to maintain 100% correlation to GL models and to ensure the injection of realistic faults into VPs. Our approach’s key aspects are: matching points across abstraction levels and selective abstraction of GL functionality using compiled-code simulation. Measurements show two orders of magnitude speed-up over RTL models and three orders of magnitude over GL models. Moreover, the speed-up increases with design size.